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Verilog Simulation Model for 28F640J5

Intel Corp. (Folsom)


Architecture:
Type :
Last Update:

Flash Memory Components Intel(R) StrataFlash(TM) Memory
Simulation Models
4/2/98 4:08:47 PM

Vendor Information


Tool Description:

This Verilog bus functional model is designed to assist customers in performing entire system simulations. By simulating an entire system before silicon samples are received, errors can be caught and fixed earlier in the design phase. This shortens customers' time to market and saves them money. Intel's models are available free of charge, but do not come with customer support. For technical support, training, and other services, customers should contact third party vendors.

Tool Features:

  • Allows faster debug, time to market

  • Enables software development in advance of hardware

  • Used in system simulations

  • Represents device functionality, timings

  • Mimics logical behavior of flash device

    • File Attachments:

    Inrev.txt - Tool in revision

    Supported Device Detail Matrix:

    		Part & Package

    		Revision

    		Status

    		Availability

    		28F640J5 - SSOP-56 ld
    28F640J5 - uBGA-56 ball

    		1.0
    1.0

    		Released
    Released

    		NOW
    NOW


    Vendor Information:


    Intel Corp. (Folsom)

    1900 Prairie City Road
    Folsom , CA 95630
    USA

    Tech : (916) 356-3104
    Email : flash@inside.intel.com
    Fax : (916) 356-2803
    Toll Free : (800) 628-8686
    BBS : (916) 356-3600
    URL : http://developer.intel.com

    Contact the vendor above for the latest Distributor information



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